The present invention relates to data storage systems, and more specifically, to an architecture that incorporates pipeline characteristics for iterative decoding of product codes.
Currently-used linear tape drives apply two-dimensional product codes for error correction coding (ECC). These product codes generally contain two orthogonally-placed component codes consisting of a C1 row code and a C2 column code. C1 and C2 codes are in general linear block codes with minimum Hamming distance d1 and d2, respectively, which may be a binary (bit-based) code, such as a binary Bose-Chaudhuri-Hocquenghem (BCH) code over Galois Field (GF) of GF(2) or a symbol-based code with symbol alphabet size Q, such as a Reed-Solomon (RS) code over GF(Q=2q) with q-bit symbols, or a nonbinary BCH code over GF(Q=2q) with q-bit symbols, etc. In storage and transmission systems, typically Q=2 (1-bit symbol, i.e., binary codes), Q=16 (4-bit symbol), Q=64 (6-bit symbol), Q=256 (8-bit symbol), Q=512 (9-bit symbol), Q=1024 (10-bit symbol), or Q=4096 (12-bit symbol), etc.
Tape storage and optical storage technologies typically use C1 and C2 codes that are RS codes, while flash memory and optical communication technologies typically use C1 and C2 codes that are binary BCH codes.
Failure to decode a product codeword, which requires successful decoding of all C1 rows and all C2 columns within a product code, leads to a temporary and/or permanent error, and the decoder for the product code (possibly an iterative decoder) does not produce a valid product codeword. In order to reduce the number of errors, iterative decoding may be used where the product codeword is decoded by repeatedly decoding the C1 codewords and C2 codewords that comprise the product code.
However, this may cause a delay in the reading of data when using conventional tape drive architectures for the data to be decoded repeatedly. It is important that when performing error correction that the tape drive is able to continuously stream data from the tape at the highest possible tape velocity while the data is being decoded. Therefore, it would be beneficial to have an architecture configured for iterative decoding, while maintaining a high-throughput.